Silicon Concept Inc, (SIC), offers a range of advanced metrology products and solutions for semiconductor, LED, Solar, FPD, Data Storage and MEMS applications. We have over 25 years experience in stress measurement, film adhesion testing, wafer topography metrology, and electrical characterization. Our latest offerings include unique technology to meet the metrology needs of 3DIC manufacturing and to monitor stress of large flat panels.
SIC has local sales and support offices in all major semiconductor clusters. Other areas are covered by a network of local representatives.
SIC offers metrology and characterization systems for front-end, back-end, as well as research and development applications.
Film adhesion testing of thin films and stacks on substrates for material evaluation.
Contact and Non-Contact sheet resistance measurement systems for implantation, diffusion, metallization, and many other applications.
Stress Hysteresis Measurement up to 500C for thermal property and stability tests of thin films in inert gas. Non-Contact Laser Scanning Technology.
Silicon Concepts is the leading manufacturer of stress measurement tools for semiconductor, MEMS, optoelectronic, and flat panel applications. Stress and wafer bow maps can be acquired over the entire wafer surface, providing process engineers means to characterize and develop new processes using different thin film materials.
The SIC 128 Series systems are room temperature, full-wafer 2D/3D stress mapping systems. 128 systems use SIC's patented non-contact Opti-Lever dual-laser auto-switching technology. Ability to scan 1000 points per inch in seconds for high resolution, high precision stress mapping on blanked and patterned wafers.
Substrate and tape total and individual thicknesses, warpage, and TTV Measurement. Able to measure with or without backing tape. For wafer back-grind and etch thinning processes control. Non-contact Echoprobe or VITE Technology. Thin film and surface roughness options.
Stress Hysteresis in vacuum or gas up to 900C for the study of annealing cycles. Thermal Desorption, Film Shrinkage, Reflectivity, and Resistivity options provide additional insight to causes of material changes with temperature. NEW: Optional wafer rotation offers unique 2D/3D mapping to study wafer deformation as a function of temperature.
Local and Lattice Stress Measurement, Die level Topography. For in-die and in-device stress and composition control.
New high speed, high accuracy non-contact characterization of thin wafers, through silicon vias (TSV), bumps, MEMS structures and novel materials. SIC 8108 VITE can be employed in the front-end and backend. It provides thickness, TTV, and topography of Si and compound materials, edge trim geometry, multilayer thickness and topography of wafers on tape, on sapphie,or on glass. Measurement of warp of highly warped wafers and measurement of thick films.
Thickness and total thickness variation (TTV) mapping system. TTV and Thickness of wafer substrate, thick layers, wafers on tape, bonded wafers, etc. Fully automated cassette to cassette system, SECS/GEM compliant. Warp, Roughness, and Thin Film Thickness measurement options.
Dedicated Film Stress mapping system with high resolution for high throughput process control. Fully automated cassette to cassette, SECS/GEM compliant 300mm Film Stress and Bow Measurement tool. Dual or single FOUP configurations available. Integrated wafer substrate thickness measurement available.